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ITC
2002
IEEE
114views Hardware» more  ITC 2002»
15 years 11 months ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
KBSE
2002
IEEE
15 years 11 months ago
SeDiTeC - Testing Based on Sequence Diagrams
In this paper we present a concept for automated testing of object-oriented applications and a tool called SeDiTeC that implements these concepts for Java applications. SeDiTeC us...
Falk Fraikin, Thomas Leonhardt
ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Constraint extraction for pseudo-functional scan-based delay testing
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Chen...
ICSE
2009
IEEE-ACM
15 years 4 months ago
Security Test Generation Using Threat Trees
Software security issues have been a major concern to the cyberspace community, so a great deal of research on security testing has been performed, and various security testing te...
Aaron Marback, Hyunsook Do, Ke He, Samuel Kondamar...
SEFM
2008
IEEE
16 years 20 days ago
Tagging Make Local Testing of Message-Passing Systems Feasible
The only practical way to test distributed messagepassing systems is to use local testing. In this approach, used in formalisms such as concurrent TTCN-3, some components are repl...
Puneet Bhateja, Madhavan Mukund