154 search results - page 18 / 31 » Limiting the power consumption of main memory |
157
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JNW
2008
15 years 6 months ago
2008
This paper presents the results of a study on the effects of data aggregation for multi-target tracking in wireless sensor networks. Wireless sensor networks are normally limited i...
132
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MICRO
2006
IEEE
16 years 2 days ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
169
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ISCAS
2005
IEEE
15 years 11 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
133
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VLSISP
2008
15 years 6 months ago
2008
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
217
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DAC
2010
ACM
15 years 10 months ago
2010
ACM
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...