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» Limiting the power consumption of main memory
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ISPASS
2010
IEEE
16 years 28 days ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
RTAS
2010
IEEE
15 years 4 months ago
Using PCM in Next-generation Embedded Space Applications
Abstract--Dynamic RAM (DRAM) has been the best technology for main memory for over thirty years. In embedded space applications, radiation hardened DRAM is needed because gamma ray...
Alexandre Peixoto Ferreira, Bruce R. Childers, Ram...
EUROPAR
2010
Springer
15 years 6 months ago
Power-Efficient Spilling Techniques for Chip Multiprocessors
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
Enric Herrero, José González, Ramon ...
ICOIN
2003
Springer
15 years 11 months ago
Scalable IP Routing Lookup in Next Generation Network
Ternary content-addressable memory has been widely used to perform fast routing lookups. It is able to accomplish the best matching prefix problem in O(1) time without considering...
Chia-Tai Chan, Pi-Chung Wang, Shuo-Cheng Hu, Chung...
IPPS
2007
IEEE
16 years 11 days ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...