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ICCAD
2007
IEEE
98views Hardware» more  ICCAD 2007»
16 years 3 months ago
Device-circuit co-optimization for mixed-mode circuit design via geometric programming
Modern processing technologies offer a number of types of devices such as high-VT , low-VT , thick-oxide, etc. in addition to the nominal transistor in order to meet system perfor...
Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong K...
SOSP
2003
ACM
16 years 3 months ago
User-level internet path diagnosis
Diagnosing faults in the Internet is arduous and time-consuming, in part because the network is composed of diverse components spread across many administrative domains. We consid...
Ratul Mahajan, Neil T. Spring, David Wetherall, Th...
SOSP
2005
ACM
16 years 3 months ago
Capturing, indexing, clustering, and retrieving system history
We present a method for automatically extracting from a running system an indexable signature that distills the essential characteristic from a system state and that can be subjec...
Ira Cohen, Steve Zhang, Moisés Goldszmidt, ...
SOSP
2007
ACM
16 years 3 months ago
Triage: diagnosing production run failures at the user's site
Diagnosing production run failures is a challenging yet important task. Most previous work focuses on offsite diagnosis, i.e. development site diagnosis with the programmers prese...
Joseph Tucek, Shan Lu, Chengdu Huang, Spiros Xanth...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 3 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson