Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltag...
Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jan...
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Pari...
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
- This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conve...
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...