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VLSID
2003
IEEE
104views VLSI» more  VLSID 2003»
16 years 7 months ago
Analyzing Soft Errors in Leakage Optimized SRAM Design
Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltag...
Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jan...
VLSID
2003
IEEE
96views VLSI» more  VLSID 2003»
16 years 7 months ago
Design Of A Universal BIST (UBIST) Structure
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Pari...
VLSID
2003
IEEE
115views VLSI» more  VLSID 2003»
16 years 7 months ago
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
W. Kuang, J. S. Yuan
ICCD
2008
IEEE
121views Hardware» more  ICCD 2008»
16 years 3 months ago
Characterization and design of sequential circuit elements to combat soft error
- This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conve...
Hamed Abrishami, Safar Hatami, Massoud Pedram
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
16 years 3 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici