With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
The fare planning problem for public transport is to design a system of fares that maximize the revenue. We introduce a nonlinear optimization model to approach this problem. It i...
Recently a bulk of research [14, 5, 15, 9] has been done on the modelling of the smallworld phenomenon, which has been shown to be pervasive in social and nature networks, and eng...
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...