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2005
Tsinghua U.
16 years 7 days ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal
OR
2005
Springer
16 years 6 days ago
Optimal Fares for Public Transport
The fare planning problem for public transport is to design a system of fares that maximize the revenue. We introduce a nonlinear optimization model to approach this problem. It i...
Ralf Borndörfer, Marika Neumann, Marc E. Pfet...
PDCAT
2005
Springer
16 years 6 days ago
Optimal Routing in a Small-World Network
Recently a bulk of research [14, 5, 15, 9] has been done on the modelling of the smallworld phenomenon, which has been shown to be pervasive in social and nature networks, and eng...
Jianyang Zeng, Wen-Jing Hsu
ASPLOS
2004
ACM
16 years 4 days ago
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
CF
2004
ACM
16 years 4 days ago
A first glance at Kilo-instruction based multiprocessors
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
Marco Galluzzi, Valentin Puente, Adrián Cri...
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