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CODES
2008
IEEE
16 years 20 days ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
CODES
2008
IEEE
16 years 20 days ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
HPDC
2008
IEEE
16 years 19 days ago
Ontological framework for a free-form query based grid search engine
If the model of free-form queries, which has proved successful for HTML based search on the Web, is made available for Grid services, it will serve as a powerful tool for scientis...
Chaitali Gupta, Rajdeep Bhowmik, Madhusudhan Govin...
CODES
2007
IEEE
16 years 16 days ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
16 years 14 days ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
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