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DAC
2008
ACM
16 years 7 months ago
Functional test selection based on unsupervised support vector analysis
Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverag...
Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Fo...
DAC
2003
ACM
16 years 7 months ago
Support vector machines for analog circuit performance representation
The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parame...
Fernando De Bernardinis, Michael I. Jordan, Albert...
DAC
2003
ACM
16 years 7 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
DAC
2005
ACM
16 years 7 months ago
Efficient SAT solving: beyond supercubes
SAT (Boolean satisfiability) has become the primary Boolean reasoning engine for many EDA applications, so the efficiency of SAT solving is of great practical importance. Recently...
Domagoj Babic, Jesse D. Bingham, Alan J. Hu
ICSE
2008
IEEE-ACM
16 years 7 months ago
Design patterns: between programming and software design
In computer science curricula the two areas programming and software engineering are usually separated. In programming students learn an object oriented language and then deepen t...
Christoph Denzler, Dominik Gruntz