62 search results - page 10 / 13 » Leakage Minimization Technique for Nanoscale CMOS VLSI |
149
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ICCAD
2009
IEEE
15 years 3 months ago
2009
IEEE
Multi-threshold CMOS (MTCMOS) is an effective powergating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS switches. However, few ex...
147
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CEC
2005
IEEE
15 years 11 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
160
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DATE
2009
IEEE
16 years 24 days ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
175
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GLVLSI
2008
IEEE
16 years 15 days ago
2008
IEEE
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
159
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ARCS
2006
Springer
15 years 9 months ago
2006
Springer
State-of-the-art technologies in very large scale integration (VLSI) allow for the realization of gates with varying energy consumptions and hence delays (i.e., processing speeds) ...