248 search results - page 37 / 50 » Layered Switching for Networks on Chip |
135
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ARC
2007
Springer
15 years 10 months ago
2007
Springer
Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical netwo...
159
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IPPS
2006
IEEE
16 years 1 days ago
2006
IEEE
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
139
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HPCA
2009
IEEE
16 years 6 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
137
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FPL
2007
Springer
16 years 5 days ago
2007
Springer
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
171
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IWSOC
2005
IEEE
15 years 11 months ago
2005
IEEE
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...