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ISCA
2003
IEEE
108views Hardware» more  ISCA 2003»
15 years 11 months ago
Effective ahead Pipelining of Instruction Block Address Generation
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
André Seznec, Antony Fraboulet
DAC
1998
ACM
15 years 10 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
JOT
2008
142views more  JOT 2008»
15 years 6 months ago
cmUML - A UML based Framework for Formal Specification of Concurrent, Reactive Systems
Complex software systems possess concurrent and reactive behaviors requiring precise specifications prior to development. Lamport's transition axiom method is a formal specif...
Jagadish Suryadevara, Lawrence Chung, R. K. Shyama...
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
16 years 6 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf
ICDCS
2009
IEEE
16 years 3 months ago
Pushing the Envelope: Extreme Network Coding on the GPU
While it is well known that network coding achieves optimal flow rates in multicast sessions, its potential for practical use has remained to be a question, due to its high compu...
Hassan Shojania, Baochun Li