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ISPASS
2007
IEEE
16 years 28 days ago
Last-Touch Correlated Data Streaming
Recent research advocates address-correlating predictors to identify cache block addresses for prefetch. Unfortunately, address-correlating predictors require correlation data sto...
Michael Ferdman, Babak Falsafi
ISVLSI
2007
IEEE
161views VLSI» more  ISVLSI 2007»
16 years 28 days ago
CMP-aware Maze Routing Algorithm for Yield Enhancement
— Chemical-Mechanical Polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This pap...
Hailong Yao, Yici Cai, Xianlong Hong
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
16 years 28 days ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
MMM
2007
Springer
105views Multimedia» more  MMM 2007»
16 years 27 days ago
Discovering User Information Goals with Semantic Website Media Modeling
In this work we present an approach to capture the total semantics in multimedia-multimodal web pages. Our research improves upon the state-ofthe-art with two key features: (1) cap...
Bibek Dev Bhattarai, Mike Wong, Rahul Singh
NOCS
2007
IEEE
16 years 27 days ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...