We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Convenience, reliability, and effectiveness of automatic memory management have long been established in modern systems and programming languages such as Java. The timeliness req...
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently ...
Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu...
Scheduling strategies for parallel and distributed computing have mostly been oriented toward performance, while striving to achieve some notion of fairness. With the increase in ...
Darin England, Jon B. Weissman, Jayashree Sadagopa...
— In this paper, we study cross-layer design for rate control in multihop wireless networks. In our previous work, we have developed an optimal cross-layered rate control scheme ...