7065 search results - page 313 / 1413 » Iterative Scheduling Algorithms |
166
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SODA
2008
ACM
15 years 8 months ago
2008
ACM
This paper presents a multicore-cache model that reflects the reality that multicore processors have both per-processor private (L1) caches and a large shared (L2) cache on chip. ...
169
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GECCO
2006
Springer
15 years 10 months ago
2006
Springer
To help unravel the structure of the universe, astronomers have developed systems which observe large clusters of objects at the same time. One such system is the 2-degree field s...
136
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AUSAI
2003
Springer
15 years 12 months ago
2003
Springer
We have recently introduced a hyper-heuristic genetic algorithm (hyper-GA) with an adaptive length chromosome which aims to evolve an ordering of low-level heuristics so as to find...
190
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APCSAC
2005
IEEE
16 years 10 days ago
2005
IEEE
Abstract. Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for ...
190
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JSSPP
2005
Springer
16 years 6 days ago
2005
Springer
Real-time applications with security requirements are emerging in various areas including government, education, and business. The security sensitive real-time applications can ta...