Sciweavers

7065 search results - page 1087 / 1413
» Iterative Scheduling Algorithms
Sort
View
ASIACRYPT
1998
Springer
15 years 11 months ago
Analysis Methods for (Alleged) RC4
Abstract. The security of the alleged RC4 stream cipher and some variants is investigated. Cryptanalytic algorithms are developed for a known plaintext attack where only a small se...
Lars R. Knudsen, Willi Meier, Bart Preneel, Vincen...
ICCAD
1996
IEEE
85views Hardware» more  ICCAD 1996»
15 years 11 months ago
Exploiting regularity for low-power design
Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized desi...
Renu Mehra, Jan M. Rabaey
ICDT
1997
ACM
74views Database» more  ICDT 1997»
15 years 11 months ago
Serializability of Nested Transactions in Multidatabases
Abstract. The correctness of nested transactions for multidatabases differs from that of at transactions in that, for nested transactions the execution order of siblings at each re...
Ugur Halici, Ismailcem Budak Arpinar, Asuman Dogac
155
Voted
EURODAC
1994
IEEE
116views VHDL» more  EURODAC 1994»
15 years 10 months ago
A performance evaluator for parameterized ASIC architectures
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...
Jie Gong, Daniel D. Gajski, Alex Nicolau
155
Voted
ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
15 years 10 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
« Prev « First page 1087 / 1413 Last » Next »