1973 search results - page 258 / 395 » Issues in the Integration of IN and TMN |
179
click to vote
DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
195
click to vote
DSN
2009
IEEE
16 years 1 months ago
2009
IEEE
Dynamic symbolic execution is a structural testing technique that systematically explores feasible paths of the program under test by running the program with different test input...
176
click to vote
GLVLSI
2009
IEEE
16 years 1 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
180
click to vote
GLVLSI
2009
IEEE
16 years 1 months ago
2009
IEEE
Recently, cooperative communication has attracted a lot of attention for its potential to increase spatial diversity. However, limited attention has been paid to the physical laye...
169
click to vote
GLVLSI
2009
IEEE
16 years 1 months ago
2009
IEEE
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...