10600 search results - page 376 / 2120 » Issues in process architecture |
205
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FPGA
2008
ACM
15 years 8 months ago
2008
ACM
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
169
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SIGCOMM
2010
ACM
15 years 7 months ago
2010
ACM
Traditionally, in-network services like firewall, proxy, cache, and transcoders have been provided by dedicated hardware middleboxes. A recent trend has been to remove the middleb...
187
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IPPS
2007
IEEE
16 years 1 months ago
2007
IEEE
This paper presents a new and retargetable method to identify patterns of instructions with direct support in coarsegrained processing elements (PEs). The method uses a three-addr...
127
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ICANN
2007
Springer
16 years 29 days ago
2007
Springer
Abstract. This paper introduces the notion of the variadic neural network (VNN). The inputs to a variadic network are an arbitrary-length list of n-tuples of real numbers, where n ...
177
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ICSOC
2007
Springer
16 years 29 days ago
2007
Springer
In this paper we present the architecture and design of an extended BPEL engine that implements the operational semantics of BPEL4SWS. BPEL4SWS is an extension of the BPEL language...