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ASAP
2006
IEEE
119views Hardware» more  ASAP 2006»
15 years 8 months ago
From Bit Level Systolic Arrays to HDTV Processor Chips
The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on sys...
John V. McCanny, Roger F. Woods, John G. McWhirter
HICSS
1999
IEEE
106views Biometrics» more  HICSS 1999»
15 years 11 months ago
Automating the Interoperation of Information Processing Tools
This paper describes an agent-based architecture designed to support the interoperation of distributed and disparate information processing tools and resources. This work is based...
Stephen Cranefield, Emanuela Moreale, Bryce McKinl...
NCA
2007
IEEE
16 years 25 days ago
Improving Network Processing Concurrency using TCPServers
Exponentially growing bandwidth requirements and slowing gains in processor speeds have led to the popularity of multiprocessor architectures. Network stack parallelism is increas...
Aniruddha Bohra, Liviu Iftode
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
16 years 5 days ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
15 years 10 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen