Sciweavers

10600 search results - page 1903 / 2120
» Issues in process architecture
Sort
View
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 12 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
FPL
2003
Springer
164views Hardware» more  FPL 2003»
15 years 12 months ago
FPGA Implementations of the RC6 Block Cipher
RC6 is a symmetric-key algorithm which encrypts 128-bit plaintext blocks to 128-bit ciphertext blocks. The encryption process involves four operations: integer addition modulo 2w ,...
Jean-Luc Beuchat
FPL
2003
Springer
100views Hardware» more  FPL 2003»
15 years 12 months ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
FPL
2003
Springer
164views Hardware» more  FPL 2003»
15 years 12 months ago
Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System
Intrusion Detection Systems such as Snort scan incoming packets for evidence of security threats. The most computation-intensive part of these systems is a text search against hund...
Ioannis Sourdis, Dionisios N. Pnevmatikatos
EDBTW
2010
Springer
15 years 11 months ago
Declarative scheduling in highly scalable systems
In modern architectures based on Web Services or Cloud Computing, a very large number of user requests arrive concurrently and has to be scheduled for execution constrained by cor...
Christian Tilgner
« Prev « First page 1903 / 2120 Last » Next »