10600 search results - page 1839 / 2120 » Issues in process architecture |
166
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Abstract--To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous res...
177
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits. One effective technique that provides real-time visibility to ...
136
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of ma...
156
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
In recent literature it has been reported that Dynamic Power Management (DPM) may lead to decreased reliability in real-time embedded systems. The ever-shrinking device sizes cont...
158
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
A key problem that arises in System-on-a-Chip (SOC) designs of today is the Chip-level Clock Tree Synthesis (CCTS). CCTS is done by merging all the clock trees belonging to differ...