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EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
15 years 10 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
SAS
1993
Springer
139views Formal Methods» more  SAS 1993»
15 years 10 months ago
Compiling FX on the CM-2
Type and effect systems provide a safe and effective means of programming high-performance parallel computers with a high-level language that integrates both functional and impe...
Jean-Pierre Talpin, Pierre Jouvelot
ASPDAC
2007
ACM
130views Hardware» more  ASPDAC 2007»
15 years 10 months ago
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses
On an SoC bus, contentions occur while different IP cores request the bus access at the same time. Hence an arbiter is mandatory to deal with the contention issue on a shared bus s...
Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing...
CANDT
2009
15 years 10 months ago
Supporting community engagement in the city: urban planning in the MR-tent
Urban design today faces complex demands. It has become a necessity to negotiate between stakeholder objectives, the expectations of citizens, and the demands of planning. In this...
Ina Wagner, Maria Basile, Lisa Ehrenstrasser, Val&...
WCNC
2010
IEEE
15 years 10 months ago
Optimality of Diagonalization of Multicarrier Multi-Hop Linear Non-Regenerative MIMO Relays
Abstract—In this paper, a multicarrier multi-hop multipleinput multiple-output (MIMO) relay system is investigated. A linear non-regenerative strategy is applied at each relay no...
Yue Rong, Yingbo Hua