555 search results - page 52 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
167
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FPL
2009
Springer
15 years 10 months ago
2009
Springer
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
152
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SIGMETRICS
2008
ACM
15 years 6 months ago
2008
ACM
Several peer-to-peer systems for live streaming have been recently deployed (e.g. CoolStreaming, PPLive, SopCast). These all rely on distributed, epidemic-style dissemination mech...
175
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...
157
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Energy-efficiency and power-awareness for electronic systems have been important design issues in hardware and software implementations. We consider the scheduling of periodic ha...
159
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ICCS
2004
Springer
15 years 11 months ago
2004
Springer
: Synchronous finite state machines are very important for digital sequential designs. Among other important aspects, they represent a powerful way for synchronizing hardware comp...