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MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
16 years 29 days ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
LCTRTS
2007
Springer
16 years 14 days ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
ISPA
2004
Springer
15 years 11 months ago
Cayley DHTs - A Group-Theoretic Framework for Analyzing DHTs Based on Cayley Graphs
Static DHT topologies influence important features of such DHTs such as scalability, communication load balancing, routing efficiency and fault tolerance. Nevertheless, it is co...
Changtao Qu, Wolfgang Nejdl, Matthias Kriesell
DIALM
2007
ACM
144views Algorithms» more  DIALM 2007»
15 years 10 months ago
Reliable Local Broadcast in a Wireless Network Prone to Byzantine Failures
Reliable broadcast can be a very useful primitive for many distributed applications, especially in the context of sensoractuator networks. Recently, the issue of reliable broadcas...
Vartika Bhandari, Nitin H. Vaidya
SC
1995
ACM
15 years 10 months ago
Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
Umakishore Ramachandran, Gautam Shah, Anand Sivasu...