2587 search results - page 136 / 518 » Intrusion Tolerant Systems |
158
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DSD
2007
IEEE
16 years 25 days ago
2007
IEEE
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
161
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ETFA
2006
IEEE
16 years 16 days ago
2006
IEEE
♦ To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its ...
IAT
2006
IEEE
16 years 16 days ago
2006
IEEE
139
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IOLTS
2006
IEEE
16 years 15 days ago
2006
IEEE
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity p...
