Sciweavers

7956 search results - page 1430 / 1592
» Into the Future
Sort
View
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 11 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 11 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
15 years 11 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
LCN
2000
IEEE
15 years 11 months ago
On Integrating Differentiated Services and UMTS Networks
Differentiated Services (DS) is currently the major approach discussed to provide network layer service differentiation in IP networks. However, the discussion mainly addresses ï¬...
Jörg Diederich, Thorsten Lohmar, Martina Zitt...
MSS
2000
IEEE
72views Hardware» more  MSS 2000»
15 years 11 months ago
The InTENsity PowerWall: A Case Study for a Shared File System Testing Framework
The InTENsity PowerWall is a display system used for high-resolution visualization of very large volumetric data sets. The display is linked to two separate computing environments...
Alex W. Elder, Thomas Ruwart, Benjamin D. Allen, A...
« Prev « First page 1430 / 1592 Last » Next »