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» Interface Design for Rationally Clocked GALS Systems
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ATAL
2007
Springer
16 years 1 days ago
An adversarial environment model for bounded rational agents in zero-sum interactions
Multiagent environments are often not cooperative nor collaborative; in many cases, agents have conflicting interests, leading to adversarial interactions. This paper presents a ...
Inon Zuckerman, Sarit Kraus, Jeffrey S. Rosenschei...
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
15 years 11 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
ISLPED
2010
ACM
169views Hardware» more  ISLPED 2010»
15 years 3 months ago
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Abstract--As a replacement for the fast-fading GloballySynchronous model, we have defined a flexible design style called GRLS, for Globally-Ratiochronous, Locally-Synchronous, whic...
Jean-Michel Chabloz, Ahmed Hemani
ICCD
2000
IEEE
94views Hardware» more  ICCD 2000»
15 years 10 months ago
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies
In system-on-a-chip design, interfacing of Intellectual Property(IP) blocks is one of the most important issues. Since most IP’s are provided by different vendors, they have dif...
Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min ...
DAC
2007
ACM
16 years 6 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...