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FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
16 years 3 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
VEE
2006
ACM
139views Virtualization» more  VEE 2006»
16 years 3 days ago
Vector LLVA: a virtual vector instruction set for media processing
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speciï¬...
Robert L. Bocchino Jr., Vikram S. Adve
VEE
2005
ACM
203views Virtualization» more  VEE 2005»
15 years 11 months ago
Inlining java native calls at runtime
We introduce a strategy for inlining native functions into JavaTM applications using a JIT compiler. We perform further optimizations to transform inlined callbacks into semantica...
Levon Stepanian, Angela Demke Brown, Allan Kielstr...
IPPS
2002
IEEE
15 years 11 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
APL
1992
ACM
15 years 10 months ago
Compiler Tools in APL
We present the design and implementation of APL Intrinsic Functions for a Finite State Machine (also known as a Finite State Automaton) which recognizes regular languages, and a P...
Robert Bernecky, Gert Osterburg