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COMSWARE
2007
IEEE
16 years 1 months ago
BARAKA: A Hybrid Simulator of SANETs
— We present BARAKA, a new simulator for SANETs. The evaluation of algorithms developed for communication and co-operation in this context is usually accomplished separately. On ...
Thomas Halva Labella, Isabel Dietrich, Falko Dress...
DATE
2007
IEEE
89views Hardware» more  DATE 2007»
16 years 1 months ago
Computing synchronizer failure probabilities
— System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchro...
Suwen Yang, Mark R. Greenstreet
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
16 years 1 months ago
System level clock tree synthesis for power optimization
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal...
IPPS
2007
IEEE
16 years 29 days ago
Splice: A Standardized Peripheral Logic and Interface Creation Engine
Recent advancements in FPGA technology have allowed manufacturers to place general-purpose processors alongside user-configurable logic gates on a single chip. At first glance, ...
Justin Thiel, Ron K. Cytron
ARCS
2007
Springer
16 years 26 days ago
Architecture for Collaborative Business Items
Sensor network technology is pushing towards integration into the business world. By using sensor node hardware to augment real life business items it is possible to capture the wo...
Till Riedel, Christian Decker, Phillip Scholl, Alb...