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» Integrating Temporal Logics
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FPGA
2010
ACM
276views FPGA» more  FPGA 2010»
16 years 3 months ago
Accelerating Monte Carlo based SSTA using FPGA
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...
Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, K...
FOSSACS
2009
Springer
16 years 1 months ago
Beyond Shapes: Lists with Ordered Data
Standard analysis on recursive data structures restrict their attention to shape properties (for instance, a program that manipulates a list returns a list), excluding properties t...
Kshitij Bansal, Rémi Brochenin, Étie...
VLSI
2007
Springer
16 years 24 days ago
Simulation of hybrid computer architectures: simulators, methodologies and recommendations
— In the future, high performance computing systems may consist of multiple multicore processors and reconfigurable logic coprocessors. Industry trends indicate that such coproc...
Pranav Vaidya, Jaehwan John Lee
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
16 years 3 days ago
The design of a low power asynchronous multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
Yijun Liu, Stephen B. Furber
GLVLSI
2003
IEEE
140views VLSI» more  GLVLSI 2003»
15 years 12 months ago
Exploiting multiple functionality for nano-scale reconfigurable systems
It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a res...
Paul Beckett