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ICS
2001
Tsinghua U.
15 years 11 months ago
Integrating superscalar processor components to implement register caching
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
Matt Postiff, David Greene, Steven E. Raasch, Trev...
SAC
2010
ACM
16 years 1 months ago
A business driven cloud optimization architecture
In this paper, we discuss several facets of optimization in cloud computing, the corresponding challenges and propose an architecture for addressing those challenges. We consider ...
Marin Litoiu, C. Murray Woodside, Johnny Wong, Joa...
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
16 years 5 days ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
CF
2010
ACM
15 years 11 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
CORR
2008
Springer
185views Education» more  CORR 2008»
15 years 6 months ago
Realizing Fast, Scalable and Reliable Scientific Computations in Grid Environments
The practical realization of managing and executing large scale scientific computations efficiently and reliably is quite challenging. Scientific computations often invo...
Yong Zhao, Ioan Raicu, Ian T. Foster, Mihael Hateg...