1624 search results - page 48 / 325 » Integrating Fault-Tolerant Techniques into the Design of Cri... |
134
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
165
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CAV
2009
Springer
16 years 6 months ago
2009
Springer
ity Abstraction for Declarative Networking Applications Juan A. Navarro P?erez, Andrey Rybalchenko, and Atul Singh Max Planck Institute for Software Systems (MPI-SWS) Declarative N...
152
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MTDT
2003
IEEE
15 years 11 months ago
2003
IEEE
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...
140
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
224
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ISCA
2010
IEEE
15 years 11 months ago
2010
IEEE
This paper presents a fundamental law for parallel performance: it shows that parallel performance is not only limited by sequential code (as suggested by Amdahl’s law) but is a...