1624 search results - page 179 / 325 » Integrating Fault-Tolerant Techniques into the Design of Cri... |
173
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NSDI
2004
15 years 7 months ago
2004
Designing a wide-area distributed hash table (DHT) that provides high-throughput and low-latency network storage is a challenge. Existing systems have explored a range of solution...
151
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CODES
2001
IEEE
15 years 10 months ago
2001
IEEE
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
202
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CLOUD
2010
ACM
15 years 11 months ago
2010
ACM
Parallel dataflow programs generate enormous amounts of distributed data that are short-lived, yet are critical for completion of the job and for good run-time performance. We ca...
175
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
159
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ASAP
2007
IEEE
15 years 8 months ago
2007
IEEE
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...