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DATE
2003
IEEE
117views Hardware» more  DATE 2003»
16 years 22 days ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
LCPC
2001
Springer
15 years 12 months ago
The Structure of a Compiler for Explicit and Implicit Parallelism
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
Seon Wook Kim, Rudolf Eigenmann
IDA
1999
Springer
15 years 11 months ago
Knowledge-Based Visualization to Support Spatial Data Mining
Data mining methods are designed for revealing significant relationships and regularities in data collections. Regarding spatially referenced data, analysis by means of data minin...
Gennady L. Andrienko, Natalia V. Andrienko
SIGGRAPH
1990
ACM
15 years 11 months ago
The accumulation buffer: hardware support for high-quality rendering
Paul Haeberli and Kurt Akeley SiliconGraphicsComputerSystems This paper describes a system architecture that supports realtime generation of complex images, efficient generation o...
Paul Haeberli, Kurt Akeley
ANSS
2004
IEEE
15 years 11 months ago
Cache Simulation Based on Runtime Instrumentation for OpenMP Applications
To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow...
Jie Tao, Josef Weidendorfer