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DAC
1994
ACM
15 years 11 months ago
Statistical Delay Modeling in Logic Design and Synthesis
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
Horng-Fei Jyu, Sharad Malik
DAC
1994
ACM
15 years 11 months ago
Fitting Formal Methods into the Design Cycle
This tutorial introduces several methods of formal hardware veri cation that could potentially have a practical impact on the design process. The measure of success in integrating...
Kenneth L. McMillan
COMPSAC
2004
IEEE
15 years 11 months ago
Real-Time Strategy and Practice in Service Grid
The emerging service grids bring together various distributed application-level services to a `market' for clients to request and enable the integration of services across di...
Hai Jin, Hanhua Chen, Jian Chen, Ping Kuang, Li Qi...
DAC
1997
ACM
15 years 11 months ago
Formal Verification of FIRE: A Case Study
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl P...
NGITS
1995
Springer
15 years 11 months ago
The TSIMMIS Approach to Mediation: Data Models and Languages
TSIMMIS—TheStanford-IBMManagerofMultipleInformationSources—isasystemforintegrating information. It offers a data model and a common query language that are designed to support ...
Hector Garcia-Molina, Dallan Quass, Yannis Papakon...