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ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
15 years 10 months ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
15 years 10 months ago
Power-aware mapping for reconfigurable NoC architectures
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
Mehdi Modarressi, Hamid Sarbazi-Azad
GLVLSI
2009
IEEE
146views VLSI» more  GLVLSI 2009»
15 years 10 months ago
A reconfigurable stochastic architecture for highly reliable computing
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan...
DSN
2004
IEEE
15 years 10 months ago
An Architectural Framework for Providing Reliability and Security Support
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...
EUROPAR
2008
Springer
15 years 8 months ago
DGSim: Comparing Grid Resource Management Architectures through Trace-Based Simulation
Abstract. Many advances in grid resource management are still required to realize the grid computing vision of the integration of a worldwide computing infrastructure for scientifi...
Alexandru Iosup, Omer Ozan Sonmez, Dick H. J. Epem...