Sciweavers

6593 search results - page 1023 / 1319
» Integrated Learning Architectures
Sort
View
DAC
2004
ACM
16 years 7 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
192
Voted
DAC
2004
ACM
16 years 7 months ago
STAC: statistical timing analysis with correlation
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
Jiayong Le, Xin Li, Lawrence T. Pileggi
DAC
2004
ACM
16 years 7 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
DAC
2004
ACM
16 years 7 months ago
A method for correcting the functionality of a wire-pipelined circuit
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Vidyasagar Nookala, Sachin S. Sapatnekar
186
Voted
DAC
2004
ACM
16 years 7 months ago
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics
Capacitance extraction is an important problem that has been extensively studied. This paper presents a significant improvement for the fast multipole accelerated boundary element...
Shu Yan, Vivek Sarin, Weiping Shi
« Prev « First page 1023 / 1319 Last » Next »