2784 search results - page 58 / 557 » Instruction Level Parallelism |
157
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ICCAD
1994
IEEE
15 years 10 months ago
1994
IEEE
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
163
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CASES
2005
ACM
15 years 8 months ago
2005
ACM
This paper presents a methodology for monitoring security in Application Specific Instruction-set Processors (ASIPs). This is a generalized methodology for inline monitoring insec...
137
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IPPS
2007
IEEE
16 years 9 days ago
2007
IEEE
This paper explores the correlation of instruction counts and cache misses to runtime performance for a large family of divide and conquer algorithms to compute the Walsh–Hadama...
157
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IEEEPACT
2002
IEEE
15 years 11 months ago
2002
IEEE
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
206
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IPPS
2010
IEEE
15 years 3 months ago
2010
IEEE
Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreadi...