2784 search results - page 51 / 557 » Instruction Level Parallelism |
142
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LCPC
1998
Springer
15 years 10 months ago
1998
Springer
Techniques for aggressive optimization and parallelization of applications can have the side-effect of introducing copy instructions, register-to-register move instructions, into t...
143
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ICCAD
2001
IEEE
16 years 2 months ago
2001
IEEE
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
159
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RELMICS
2005
Springer
15 years 11 months ago
2005
Springer
Abstract. As part of a larger project, we have built a declarative assembly language that enables us to specify multiple code paths to compute particular quantities, giving the ins...
172
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ISPAN
2000
IEEE
15 years 10 months ago
2000
IEEE
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
123
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IEEEPACT
2007
IEEE
16 years 8 days ago
2007
IEEE
Performance auditing is an online optimization strategy that empirically measures the effectiveness of an optimization on a particular code region. It has the potential to greatly...