2784 search results - page 409 / 557 » Instruction Level Parallelism |
211
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NOCS
2007
IEEE
16 years 22 days ago
2007
IEEE
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
142
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JSSPP
2007
Springer
16 years 17 days ago
2007
Springer
Performance evaluation in multi-cluster processor co-allocation - like in many other parallel job scheduling problems- is mostly done by computing the average metric value for the ...
216
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CCGRID
2006
IEEE
16 years 15 days ago
2006
IEEE
— Geometric shape modeling becomes increasingly complex and resource-demanding task. In this paper we propose a method to leverage the power of Grid to provide users with high-pr...
181
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CODES
2006
IEEE
16 years 15 days ago
2006
IEEE
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
158
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DATE
2006
IEEE
16 years 15 days ago
2006
IEEE
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...