2784 search results - page 225 / 557 » Instruction Level Parallelism |
175
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CF
2004
ACM
16 years 1 days ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
152
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IEEEPACT
2003
IEEE
15 years 12 months ago
2003
IEEE
This paper discusses a register bank assignment problem for a popular network processor--Intel's IXP. Due to limited data paths, the network processor has a restriction that ...
193
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ADAEUROPE
2010
Springer
15 years 11 months ago
2010
Springer
Now that multicore microprocessors have become a commodity, it is natural to think about employing them in all kinds of computing, including high-reliability embedded real-time sy...
172
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ISSS
1998
IEEE
15 years 11 months ago
1998
IEEE
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
176
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ISCA
1994
IEEE
15 years 10 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...