2784 search results - page 153 / 557 » Instruction Level Parallelism |
145
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JCIT
2007
15 years 6 months ago
2007
Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propo...
208
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CC
2012
Springer
14 years 2 months ago
2012
Springer
Abstract. Data-parallel languages like OpenCL and CUDA are an important means to exploit the computational power of today’s computing devices. In this paper, we deal with two asp...
189
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RSP
2005
IEEE
16 years 1 days ago
2005
IEEE
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
235
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FCCM
2011
IEEE
14 years 10 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
186
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ICDCS
2008
IEEE
16 years 27 days ago
2008
IEEE
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...