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FPT
2005
IEEE
163views Hardware» more  FPT 2005»
16 years 14 days ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
INFOCOM
2003
IEEE
16 years 3 days ago
Improved BGP Convergence via Ghost Flushing
— In [1], [2] it was noticed that sometimes it takes BGP a substantial amount of time and messages to converge and stabilize following the failure of some node in the Internet. I...
Anat Bremler-Barr, Yehuda Afek, Shemer Schwarz
DATE
2010
IEEE
184views Hardware» more  DATE 2010»
15 years 12 months ago
An analytical method for evaluating Network-on-Chip performance
Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and becom...
Sahar Foroutan, Yvain Thonnart, Richard Hersemeule...
VRST
2000
ACM
15 years 11 months ago
DEVA3: architecture for a large-scale distributed virtual reality system
In this paper we present the work undertaken by the Advanced Interfaces Group at the University of Manchester into the design and development of a system to support large numbers ...
Steve Pettifer, Jonathan Cook, James Marsh, Adrian...
ICDCS
1999
IEEE
15 years 11 months ago
The Inter-group Router Approach to Scalable Group Composition
This paper examines the problem of building scalable, fault-tolerant distributed systems from collections of communicating process groups, while maintaining well-defined end-to-en...
Scott Johnson, Farnam Jahanian, Jigney Shah