— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
This paper analyzes a network-baseddenial of service attack for IP (Internet Protocol) based networks. It is popularly called SYN flooding. It works by an attacker sending many T...
Christoph L. Schuba, Ivan Krsul, Markus G. Kuhn, E...
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
Feature trees have been used to accommodate records in constraint programming and record like structures in computational linguistics. Feature trees model records, and feature cons...
This report analyzes two popular heuristics for ensuring packet integrity in ATM switching systems. In particular, we analyze the behavior of packet tail discarding, in order to u...