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» Incremental reconfiguration for pipelined applications
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ISNN
2007
Springer
16 years 5 days ago
Hybrid Pipeline Structure for Self-Organizing Learning Array
In recent years, many efforts have been put in applying the concept of reconfigurable computing to neural networks. In our previous pursuits, an innovative self-organizing learning...
Janusz A. Starzyk, Mingwei Ding, Yinyin Liu
FPL
2006
Springer
129views Hardware» more  FPL 2006»
15 years 9 months ago
Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays
We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools p...
Florian Stock, Andreas Koch
FCCM
2008
IEEE
115views VLSI» more  FCCM 2008»
16 years 15 days ago
Simultaneous Retiming and Placement for Pipelined Netlists
Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architecture...
Kenneth Eguro, Scott Hauck
DAC
2009
ACM
16 years 7 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
ERSA
2009
146views Hardware» more  ERSA 2009»
15 years 3 months ago
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...