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DAC
2005
ACM
15 years 8 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
CIDR
2007
111views Algorithms» more  CIDR 2007»
15 years 8 months ago
Moirae: History-Enhanced Monitoring
In this paper, we investigate the benefits and challenges of integrating history into a near-real-time monitoring system; and present a general purpose continuous monitoring engi...
Magdalena Balazinska, YongChul Kwon, Nathan Kuchta...
CAL
2006
15 years 6 months ago
Probabilistic counter updates for predictor hysteresis and bias
Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor de...
Nicholas Riley, Craig B. Zilles
TCAD
2010
121views more  TCAD 2010»
15 years 1 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
VIS
2007
IEEE
60views Visualization» more  VIS 2007»
16 years 8 months ago
Navigating in a Shape Space of Registered Models
New product development involves people with different backgrounds. Designers, engineers, and consumers all have different design criteria, and these criteria interact. Early conce...
Randall C. Smith, Richard Pawlicki, István Kók...