We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we...
The design phase of any real-time system requires balancing the limited computational resources against the functional requirements and the performance of the application. The opt...
During language evolution, compiler construction is usually d along two dimensions: defining new abstract syntax tree (AST) classes, or adding new operations. In order to facilita...
Xiaoqing Wu, Suman Roychoudhury, Barrett R. Bryant...
RSVP is a reservation setup protocol designed specifically to support QoS signaling in the Internet. However, RSVP end-to-end signaled QoS for the Internet has not become a reali...
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...