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VLSID
2007
IEEE
126views VLSI» more  VLSID 2007»
16 years 7 months ago
An ECO Technique for Removing Crosstalk Violations in Clock Networks
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama ...
VLSID
2006
IEEE
148views VLSI» more  VLSID 2006»
16 years 7 months ago
Efficient Design and Analysis of Robust Power Distribution Meshes
With increasing design complexity, as well as continued scaling of supplies, the design and analysis of power/ground distribution networks poses a difficult problem in modern IC d...
Puneet Gupta, Andrew B. Kahng
VLSID
2002
IEEE
172views VLSI» more  VLSID 2002»
16 years 7 months ago
Improvement of ASIC Design Processes
With device counts on modern-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this con...
Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
16 years 7 months ago
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like data path alignment, I/O connec...
Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
VLDB
2007
ACM
137views Database» more  VLDB 2007»
16 years 7 months ago
Improving Data Quality: Consistency and Accuracy
Two central criteria for data quality are consistency and accuracy. Inconsistencies and errors in a database often emerge as violations of integrity constraints. Given a dirty dat...
Gao Cong, Wenfei Fan, Floris Geerts, Xibei Jia, Sh...