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VLSID
2007
IEEE
126views VLSI» more  VLSID 2007»
16 years 7 months ago
An ECO Technique for Removing Crosstalk Violations in Clock Networks
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama ...
166
Voted
VLSID
2005
IEEE
128views VLSI» more  VLSID 2005»
16 years 7 months ago
On-Line Synthesis for Partially Reconfigurable FPGAs
An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-l...
Renqiu Huang, Ranga Vemuri
191
Voted
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
16 years 28 days ago
Layout driven data communication optimization for high level synthesis
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...
Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer...
185
Voted
IPPS
2006
IEEE
16 years 27 days ago
A framework to develop symbolic performance models of parallel applications
Performance and workload modeling has numerous uses at every stage of the high-end computing lifecycle: design, integration, procurement, installation and tuning. Despite the trem...
Sadaf R. Alam, Jeffrey S. Vetter
RTAS
2006
IEEE
16 years 26 days ago
An Interface Algebra for Real-Time Components
We present an assume-guarantee interface algebra for real-time components. In our formalism a component implements a set of task sequences that share a resource. A component inter...
Thomas A. Henzinger, Slobodan Matic