As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Abstract. Software engineering activities in the Industry has come a long way with various improvements brought in various stages of the software development life cycle. The comple...
R. Selvarani, T. R. Gopalakrishnan Nair, Muthu Ram...
Optimistic parallel discrete event simulation (PDES) uses a state history trail to support rollback. State saving strategies range from making a complete copy of a model’s state...
Fabian Gomes, Brian Unger, John G. Cleary, Steve F...
We present an efficient, fully automated algorithm to assemble ESTs into full-length cDNA sequences that represent the complete coding regions of a gene. Our EST clustering algori...
Arthur Grossman, Charles Hauser, Hilary J. Holz, J...
We report on our experience from design and implementation of a powerful map application for managing, querying and visualizing evolving locations of moving objects. Instead of bu...
Kostas Patroumpas, Evi Kefallinou, Timos K. Sellis