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DFT
1999
IEEE
75views VLSI» more  DFT 1999»
15 years 11 months ago
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths
Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process...
Yiorgos Makris, Alex Orailoglu
ECRTS
1999
IEEE
15 years 11 months ago
Scheduling coprocessor for enhanced least-laxity-first scheduling in hard real-time systems
Scheduling time impact on system performance increases especially when using dynamic priority algorithms, because of the enlarged computational effort at runtime. This overhead ca...
Jens Hildebrandt, Frank Golatowski, Dirk Timmerman...
EUROMICRO
1999
IEEE
15 years 11 months ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen
PPOPP
1999
ACM
15 years 11 months ago
Automatic Node Selection for High Performance Applications on Networks
A central problem in executing performance critical parallel and distributed applications on shared networks is the selection of computation nodes and communication paths for exec...
Jaspal Subhlok, Peter Lieu, Bruce Lowekamp
ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
15 years 11 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim